View HM5117400BS-6_649390.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM5117400B Series
4,194,304-word 4-bit Dynamic Random Access Memory
ADE-203-369A (Z) Rev. 1.0 Nov. 15, 1995 Description
The Hitachi HM5117400B is a CMOS dynamic RAM organized 4,194,304 word 4 bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117400B offers Fast Page Mode as a high speed access mode.
Features
Single 5 V ( 10%) High speed Access time : 60 ns/ 70 ns/ 80 ns (max) Low power dissipation Active mode : 605 mW/550 mW/495 mW(max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) 3 variations of refresh -only refresh -beforerefresh Hidden refresh Battery backup operation (L-version) Test function 16-bit parallel test mode
This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5117400B Series
Ordering Information
Type No. HM5117400BS-6 HM5117400BS-7 HM5117400BS-8 HM5117400BLS-6 HM5117400BLS-7 HM5117400BLS-8 HM5117400BTS-6 HM5117400BTS-7 HM5117400BTS-8 HM5117400BLTS-6 HM5117400BLTS-7 HM5117400BLTS-8 Access Time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB)
Pin Arrangement
HM5117400BS/BLS Series HM5117400BTS/BLTS Series
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
VCC I/O1 I/O2
1 2 3 4 5
26 25 24 23 22 21
VSS I/O4 I/O3
NC
6
A9
NC
6
A9
A10 A0 A1 A2 A3 V
CC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
A10 A0 A1 A2 A3 VCC
8 9 10 11 12 13
19 18 17 16 15 14
A8 A7 A6 A5 A4 VSS
(Top view)
(Top view)
2
HM5117400B Series
Pin Description
Pin Name A0 to A10 A0 to A10 I/O1 to I/O4 Function Address input Refresh address input Data input/data output Row address strobe Column address strobe Write enable Output enable VCC VSS NC Power supply (+5 V) Ground No connection
3
HM5117400B Series
Block Diagram
I/O 4 I/O Buffer 4
I/O 3 I/O Buffer 3
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. &
I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O
bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. &
I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O
bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Column decoder & driver
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
Column decoder & driver
Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus
I/O Buffer 2 I/O 2
I/O Buffer 1 I/O 1
Address A0 to A10
4
HM5117400B Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70 C)
Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to V SS Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1
DC Characteristics (Ta = 0 to +70 C, VCC = 5 V
HM5117400B -6 Parameter Operating current Standby current
*1, *2
10%, VSS = 0 V)
-8
-7 Max Min 110 2 -- --
Symbol Min I CC1 I CC2 -- --
Max Min 100 2 -- --
Max Unit Test Conditions 90 2 mA mA t RC = min TTL interface , = VIH Dout = High-Z CMOS interface , V CC - 0.2V Dout = High-Z CMOS interface , V CC - 0.2V Dout = High-Z
--
1
--
1
--
1
mA
Standby current (L-version)
I CC2
--
150
--
150
--
150
A
5
HM5117400B Series
DC Characteristics (Ta = 0 to +70 C, VCC = 5 V
HM5117400B -6 Parameter -only refresh current Standby current -beforecurrent
*1 *2
10%, VSS = 0 V)
-8
-7 Max Min 110 5 110 80 350 -- -- -- -- --
Symbol Min I CC3 I CC5 refresh I CC6 -- -- -- -- --
Max Min 100 5 100 70 350 -- -- -- -- --
Max Unit Test Conditions 90 5 90 65 350 mA mA mA mA A t RC = min = VIH, Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s t RAS 0.3 s 0V Vin 7V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA = VIL
Fast page mode current *1, *3 I CC7 Battery backup current I CC10
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH.
Capacitance (Ta = 25 C, V CC = 5 V
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out)
10%)
Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout.
6
HM5117400B Series
AC Characteristics (Ta = 0 to +70 C, VCC = 5 V
Test Conditions Input rise and fall time: 5 ns Input timing reference levels : 0.8 V, 2.4 V Output load : 2 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5117400B -6 Parameter Random read or write cycle time precharge time precharge time pulse width pulse width Row address setup time Row address hold time Column address setup time Column address hold time to delay time Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RSH t CSH t CRP t OED t DZO t DZC tT 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- -7 Min 130 50 10 Max -- -- -- -8 Min 150 60 10 Max -- -- -- Unit Notes ns ns ns
10%, VSS = 0 V)*1, *2, *18, *19
10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 15 20 15 18 70 5 18 0 0 3
10000 80 10000 20 -- -- -- -- 52 35 -- -- -- -- -- -- 50 0 10 0 15 20 15 20 80 5 20 0 0 3
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
to column address delay time t RAD hold time hold time to precharge time
to Din delay time delay time from Din delay time from Din Transition time (rise and fall)
7
HM5117400B Series
Read Cycle
HM5117400B -6 Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time to Read command hold time to Column address to Column address to to output in low-Z Output data hold time Output data hold time from Output buffer turn-off time Output buffer turn-off to to Din delay time lead time lead time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD -- -- -- -- 0 0 0 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 0 40 40 0 3 3 -- -- 20 Max 80 20 40 20 -- -- -- -- -- -- -- -- 15 15 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20
Write Cycle
HM5117400B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to Write command to Data-in setup time Data-in hold time lead time lead time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 15 15 14
8
HM5117400B Series
Read-Modify-Write Cycle
HM5117400B -6 Parameter Read-modify-write cycle time to to delay time delay time delay time Symbol Min t RWC t RWD t CWD t AWD t OEH 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- -8 Min 205 110 50 70 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Column address to hold time from
Refresh Cycle
HM5117400B -6 Parameter Symbol Min 5 10 0 10 0 Max -- -- -- -- -- -7 Min 5 10 0 10 0 Max -- -- -- -- -- -8 Min 5 10 0 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns
setup time (CBR refresh cycle) t CSR hold time (CBR refresh cycle) t CHR setup time (CBR refresh cycle) t WRP hold time (CBR refresh cycle) precharge to hold time t WRH t RPC
Fast Page Mode Cycle
HM5117400B -6 Parameter Fast page mode cycle time Fast page mode Access time from hold time from pulse width precharge Symbol Min t PC t RASP t CPA 40 -- -- 35 Max -- -7 Min 45 -- 40 Max -- -8 Min 50 -- 45 Max -- Unit Notes ns 16 9, 17, 20
100000 -- 35 --
100000 -- 40 --
100000 ns 45 -- ns ns
precharge t CPRH
9
HM5117400B Series
Fast Page Mode Read-Modify-Write Cycle
HM5117400B -6 Parameter Fast page mode read-modify-write cycle time delay time from Symbol Min t PRWC 85 60 Max -- -- -7 Min 96 68 Max -- -- -8 Min 105 75 Max -- -- Unit Notes ns ns 14
precharge t CPW
Test Mode Cycle *19
HM5117400B -6 Parameter Test mode Test mode setup time hold time Symbol Min t WTS t WTH 0 10 Max -- -- -7 Min 0 10 Max -- -- -8 Min 0 10 Max -- -- Unit Notes ns ns
Refresh
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Note 2048 cycles 2048 cycles
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
10
HM5117400B Series
10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + t CAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operationg parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to leading edge in early write cycles and to leading edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. must disable output buffer prior to applying data to 18. In delayed write or read-modify-write cycles, the device. After is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance); if tOEH < tCWL, invalid data will be out at each I/O. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don't care during test mode. Test mode is set by performing -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. -beforeTo get out of test mode and enter a normal operation mode, perform either a regular refresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21 XXX: H or L (H: V IH (min) VIN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout
11
HM5117400B Series
Timing Waveforms *21
Read Cycle
t RC t RAS t RP
t CSH t RCD tT t RSH t CAS
t CRP
t RAD t ASR t ASC
t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
t DZC
t CDD
Din
High-Z
t DZO
t OEA
t OED
t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO
12
HM5117400B Series
Early Write Cycle
t RC t RAS t RP
t CSH t RCD tT t RSH t CAS
t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
t DS
t DH
Din
Din
Dout
High-Z** * ** t WCS : H or L t WCS (min)
13
HM5117400B Series
Delayed Write Cycle*18
t RC t RAS
t RP
t CSH t RCD tT t RSH t CAS
t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column t CWL t RWL t WP
t RCS
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO
t OEZ t CLZ High-Z Invalid Dout
Dout
14
HM5117400B Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
tT t RCD t CAS t CRP
t RAD t ASR tRAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
t DZC t DS Din
High-Z
t DH
Din
t DZO
t OED t OEA
t OEH
t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
15
HM5117400B Series
-Only Refresh Cycle
t RC t RAS t RP
tT t CRP t RPC t CRP
t ASR Address t OFF Dout
t RAH Row
High-Z
* Refresh Address A0 - A10 (RA0 - RA10) ** , : H or L
16
HM5117400B Series
-BeforeRefresh Cycle
t RC t RP t RAS t RP
t RPC
t CSR tT
t CHR
t RPC
t CRP
t CP
t WRP
t WRH
t CP
Address t OFF Dout High-Z
* : H or L
17
HM5117400B Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
tT t RSH t RCD t CHR t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column t WRP t RCS t RRH t WRH
t WRP
t WRH
t DZC High-Z Din
t CDD
t DZO t OEA
t OED
t CAC t AA t RAC t CLZ Dout Dout t OFF t OH
t OEZ t OHO
18
HM5117400B Series
Fast Page Mode Read Cycle
t RASP t CPRH t RP
tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t RAD t ASR t RAH Address Row
t CAL t ASC t CAH Column 1
t CAL t ASC t CAH Column 2
t RAL t CAL t ASC t CAH Column N
t RCS tRCS tRCH tRCH
t RCS
t RRH t RCH
t DZC t CDD Din t DZO High-Z t OED
t DZC t CDD High-Z t DZO t OED
t DZC t CDD High-Z t DZO t OED
t RAC t AA t OEA t CAC t CLZ Dout
t CPA t OH t AA t OHO t OEA
t OH
t CPA t AA t OHO t OFF t OEZ t OEA t CAC t CLZ Dout N
t OH t OHO t OFF t OEZ
t OFF t CAC t OEZ t CLZ Dout 1 Dout 2
19
HM5117400B Series
Fast Page Mode Early Write Cycle
t RASP t RP
tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z** * ** t WCS : H or L t WCS (min)
20
HM5117400B Series
Fast Page Mode Delayed Write Cycle *18
t RASP t RP
tT t CSH t RCD t CAS
t CP t PC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL
t WP t DZC t DS t DH Din t DZO t OED t OEH Din 1 t DZO
t WP t DZC t DS t DH Din 2 t DZO t OED t OEH
t WP t DZC t DS t DH Din N t OED t OEH
t CLZ t OEZ Dout
Invalid Dout
t CLZ t OEZ
t CLZ t OEZ High-Z
Invalid Dout Invalid Dout
21
HM5117400B Series
Fast Page Mode Read-Modify-Write Cycle *18
t RASP t RP
tT t CP t RCD t CAS
t PRWC t CP t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t CWL t RCS t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t RCS
t WP t DZC t DS t DH
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din t DZO t OED
Din 1 t DZO t OEH
t OEH
t OHO t AA t OEA t CAC t AA t CPA t OEZ t OEA t CAC
t OHO t AA t CPA t OEZ t OEA t CAC
t OHO
t RAC t CLZ Dout Dout 1
t CLZ
t CLZ
t OEZ High-Z
Dout 2
Dout N
22
HM5117400B Series
Test Mode Cycle *19
*,** Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
* CBR or
-only refresh : H or L
** Address, Din,
23
HM5117400B Series
Test Mode Set Cycle
t RC t RP t RAS t RP
t RPC
t CSR tT
t CHR
t RPC
t CRP
t CP
t WTS
t WTH
t CP
Address t OFF High-Z
Dout
24
HM5117400B Series
Package Dimensions
HM5117400BS/BLS Series (CP-26/24DB)
16.90 17.27 Max 21 19
Unit: mm
26
14
1
68 0.74
13
1.30 Max
0.43 0.10 0.10
2.54 1.27
6.71 0.25
HM5117400BTS/BLTS Series (TTP-26/24DA)
17.14 17.54 Max 21 19
Unit: mm
26
14 7.62
1 0.40 0.10
68 1.27 0.21
M
13 9.22 0.2 0 - 5
1.20 Max
0.10 1.15 Max
0.145 -0.025
0.08 Min 0.18 Max 0.68 0.50 0.10
+0.075
25

▲Up To Search▲

Price & Availability of HM5117400BS-6

	To Download HM5117400BS-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .